how can we use the clockwizard to genreate a clock signal whose frequency rate is 51.2Mhz (while the input for the clock wizard is the dac_2_clk port)Ģ. Now we want to extract from this clock signal also a signal with rate of 51.2Mhz (divide the frequency by two), we thought that we can achive it by using clocking wizard whose input is the dac_2_clk but when compiling the block diagram we recieve errors of constraint violations which belong to private constraints which belong to the adrv9001.ġ. Our worked with the reference design involves work with the TES support software for adrv9001 and with it we generate a profile with the following configurations as below:Īs you can see, when configuring the sampling rate in the TES as a result the outport of the axi_adrv9001 (meaning dac_2_clk) generate a "clock" signal in approximatly 102.4 Mhz we also using your reference design that you provide on git (the reference design contain the adrv9001 IP block). Hi all, we are using a custom board which consist of the adrv9002 RF card and the 7z035.
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